(1) Field of the Invention
The invention relates to a method and resulting structure to form dynamic random access memory (DRAM) cell array and peripheral circuits integrated circuits and more particularly to the formation of such DRAM structures which have low leakage and long retention time characteristics.
(2) Description of the Prior Art
Dynamic random access memories (DRAMs) store information by placing a desired voltage on a storage capacitor. The capacitor is thus charged or discharged. The stored voltage is normally at one of two levels, referred to as the binary "1" and "0" levels. The charge is transferred into or out of the storage capacitor by means of an switch transistor. The access transistor is typically a metal oxide semiconductor field effect transistor (MOSFET), wherein a voltage placed on the gate controls the conduction of charge through the channel between the source and drain electrodes.
DRAMs by their nature require periodic refreshing of the information stored in the cells. This refreshing is needed because of the leakage of the charge stored in the capacitor. There are various leakage mechanisms, such as from the capacitor to the substrate or through the switch transistor. Workers in the field have long worked upon this problem to give the desired characteristics of low leakage and long charge retention (hold) time in DRAM integrated circuits. One usual approach is to provide circuit improved circuit designs such as shown by Kirsch et al U.S. Pat. No. 4,679,172. Other approaches include that by K. Sawada et al, who used a self-aligned refresh scheme, namely a leak sensor, to ease the hold time control issue as published in the 1986 Symposium on VLSI Technology, May 28-30, 1986, in San Diego, pp. 85-86. However, these circuit improvements are at the expense of chip size, design complexity, etc.
As the progress of the DRAMs to ever smaller feature sizes and larger memories on a single integrated circuit chip, unexpected anomalous leakage problems were found. D. S. Yaney and C. Y. Lu et al first described such a leakage problem in their "A META-STABLE LEAKAGE PHENOMENON IN DRAM CHARGE STORAGE-VARIABLE HOLD TIME" published at the IEDM in Washington, D. C. Dec. 6-9, 1987 pages 336-339. The new leakage phenomenon which was called variable hold time (VHT). Stable periods last from seconds to hours and are punctuated by nearly instantaneous transitions. Physical investigation evidence in many cases uncovered a silicon material defect present in the offending cell, according to the authors. These anomalous leakage problems were also reported and studied by P. J. Restle et al, in a number of technologies by a variety of manufactures, as published at IEDM in San Francisco, December 1992, pp. 807-810, and including both trench capacitor and stacked capacitor DRAM chips.
There are two types of DRAM memory array cells that are used in the technology. One type is the MOSFET in combination with a stacked storage capacitor such as describe in R. Lee U.S. Pat. No. 5,066,606; Chan et al U.S. Pat. No. 5,116,776 and Jeong-Gyoo U.S. Pat. No. 5,155,056. The other type is the MOSFET in combination with a trench capacitor such as described in Ho et al U.S. Pat. No. 4,252,579; Tsuchiya U.S. Pat. No. 4,734,384; Chritchlow et al U.S. Pat. No. 4,873,205; Nitayama U.S. Pat. No. 4,784,969; Ogura et al U.S. Pat. No. 4,798,794; Nicky C. C. Lu et al "A SUBSTRATE-PLATE TRENCH-CAPACITOR (SPT) MEMORY CELL FOR DYNAMIC RAM'S" published in IEEE J. of Solid-State Circuits, Vol SC-21, No. 5, October 1986; and B. W. Shen et al "SCALABILITY OF A TRENCH CAPACITOR CELL FOR 64 MBIT DRAM" published in 1989 IEDM Technical Digest pages 27-30. Of these patents or papers address only the above cited B. W. Shen et al paper discusses the problem of leakage as the DRAM product technology moves to smaller and smaller devices. Shen et al discusses the trench capacitor leakage problem and solves the problem by raising the substrate concentration at the risk of the trench wall diode breakdown.
It is an object of this invention to provide methods which will result in the lowest possible leakage and the longest possible retention (hold) time in a DRAM array cell.
It is a further object of this invention to provide a method which uses only lightly doped ion implanted regions in the cell array of a DRAM structure and which are then heated to completely anneal the damage caused by the ion implantation.
It is a still further object of this invention to provide a DRAM integrated circuit structure which as lightly doped ion implanted regions which have been annealed in the cell array with outdiffused highly doped contacts in the lightly doped node regions and bit line regions of the cell array whereby the lowest possible leakage and the longest possible retention (hold) time, with minimum variable hold time (VHT) anomalous phenomenon, in a DRAM array cell is achieved.